1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having static memory cells.
2. Description of the Background Art
An SRAM (Static Random Access Memory) as one of typical semiconductor memory devices is a RAM which does not need refresh operation for holding stored data. A memory cell in an SRAM has a configuration that a flip flop obtained by cross coupling two inverters each made of a load element and a driver transistor is connected to a pair bit lines via access transistors.
In a memory cell in an SRAM, potential states of two storage nodes in a flip flop correspond to stored data. For example, when potentials of two storage nodes correspond to an H logical high) level and an L (logical low) level, the state corresponds to storage data of “1” and the other state corresponds to storage data of “0”. Data on the cross-coupled storage nodes is in a bi-stable state which is maintained as long as a power source voltage is supplied.
When data is written in a memory cell in an SRAM, complementary voltages are applied to a pair of bit lines in correspondence with write data, a word line is made active, and access transistors are turned on, thereby setting a state of a flip flop. On the other hand, data is read by activating a word line, turning on access transistors, transmitting the potentials of the two storage nodes to the pair of bit lines, and detecting a potential change in the bit line pair.
The SRAM also has a bit line precharge circuit for precharging a bit line pair. The bit line precharge circuit is constructed by an N-channel MOS transistor, and precharges a bit line pair to the potential of power source voltage Vcc-Vth during the period in which the precharge instruction is received. Vth denotes a threshold voltage of an N-channel MOS transistor as a component of the bit line precharge circuit.
Hitherto, in order to prevent storage data from being destroyed at the time of reading operation, a memory cell in an SRAM is designed so that a current drivability ratio (also called “cell ratio” or “β ratio”) between a driver transistor and an access transistor becomes 2.5 to 3 or higher. The cell ratio is set for the reason that when a word line is activated at the time of reading data, electric charges are supplied from a bit line to a storage node in a ground potential. If a driver transistor cannot discharge the supplied electric charges with a sufficient drive power, the potential of the storage node increases due to the supplied electric charges. Therefore, when the other driver transistor is turned on, the stored data is destroyed.
Consequently, the gate width of the driver transistor has to be larger than that of an access transistor in an SRAM. It increases the size of the memory cell in an SRAM.
Japanese Patent Laying-Open No. 63-128662 discloses an SRAM in which the cell ratio can be set to 1 or around 1 (hereinafter, also referred to as “ratioless”), thereby realizing reduction in the area of a memory cell. The SRAM has a flip flop type sense amplifier connected to a bit line pair. The sense amplifier is activated in a short period between time when stored data is read onto a bit line pair after a data reading operation is started and time when the stored data is destroyed due to the ratioless configuration, amplifies the read data, and writes the amplified data again into the memory cell. In such a manner, the SRAM in which stored data is not destroyed even when the ratioless configuration is employed is realized.
In the SRAM, although there is a problem such that the size of a memory cell increases, from the viewpoint of improvement in reading speed, the current drivability of the driver transistor is preferred to be higher. However, when the current drivability of the driver transistor is increased too much, impedance when the driver transistor is conductive becomes too low and a problem such that data cannot be written occurs. On the contrary, when the current drivability of the driver transistor is lowered so that data is easily written, as described above, stored data is destroyed at the time of reading operation.
An SRAM solving such a problem is disclosed in Japanese Patent Laying-Open No. 62-257698. In the SRAM, a capacitor is connected between the drain of a driver transistor and a predetermined potential. With the configuration, reading speed of stored data can be improved by using a discharge state of the capacitor and stored data can be prevented from being destroyed in a reading operation by electric charges accumulated in the capacitor.
In recent years, as IT (Information Technology) dramatically develops, reduction in size and improvement in performance of various electron devices is in increasing demand. A semiconductor memory device mounted on an electron device is also requested to satisfy both higher packing density and higher performance (higher processing speed and lower power consumption).
It can be said that the SRAM disclosed in Japanese Patent Laying-Open No. 63-128662 realizes the ratioless configuration and is adapted to realize higher packing density. However, the reading operation in the SRAM is destructive reading that data stored in a memory cell is once destroyed. In a reading operation, an operation of writing storage data again into a memory cell from the outside of the memory cell is necessary. The rewriting operation has to be executed on all of memory cells connected to a word line activated. Consequently, in the SRAM, further increase in processing speed and further reduction in power consumption cannot be realized.
For the past several years, with the background of improvement in portability and energy saving of an electronic device, particularly, the needs for lower power consumption in a semiconductor memory device are increasing. Since the power consumption is proportional to the square of a power source voltage, to realize lower power consumption, it is most effective to lower the power source voltage. Therefore, a semiconductor memory device newly to be proposed is naturally expected to be used with a lower voltage and is requested to achieve high performance even with a lower voltage.
Conventional SRAMs including SRAMs disclosed in Japanese Patent Laying-Open No. 63-128662 and Japanese Patent Laying-Open No. 62-257698 cannot sufficiently deal with a lower voltage. Specifically, for example, when an external power source voltage is 1.8 V and the threshold voltage of an access transistor and a driver transistor constructing a memory cell is 1.0 V, in a conventional SRAM, the potential of a storage node of the memory cell can be increased only to 0.8 V at the maximum and the driver transistor cannot be turned on.
Although it can be considered to decrease the threshold voltage of the transistor, if the threshold voltage is decreased, a leak current in an OFF state increases and power consumption in a standby mode increases. Therefore, a conventional SRAM cannot sufficiently deal with lower power consumption.
Further, although the SRAM disclosed in Japanese Patent Laying-Open No. 62-257698 can realize improvement in reading speed and prevention of destructive reading, a capacitor provided has to be charged/discharged for a writing operation. Consequently, time required for the writing operation increases by the amount. As the voltage is decreasing, time required for charging/discharging the capacity increases, so that it becomes difficult to realize higher processing speed of the semiconductor memory device.